436 search results - page 15 / 88 » Benchmarking and hardware implementation of JPEG-LS |
DDECS
2009
IEEE
14 years 2 months ago
2009
IEEE
— We propose a novel synthesis method of a dual-rail asynchronous two-level logic of reduced cost. It is based on a model that operates under so called modified weak constraints....
DATE
2010
IEEE
14 years 22 days ago
2010
IEEE
Abstract—Behavioral synthesis is the compilation of an Electronic system-level (ESL) design into an RTL implementation. We present a suite of optimizations for equivalence checki...
ISCA
1994
IEEE
13 years 11 months ago
1994
IEEE
This paper evaluates the tradeoffs involved in the design of the software-extended memory system of Alewife, a multiprocessor architecturethat implements coherentsharedmemorythrou...
DATE
2008
IEEE
14 years 2 months ago
2008
IEEE
Reed Solomon (RS) codes are used in a variety of (wireless) communication systems. Although commonly implemented in dedicated hardware, this paper explores the mapping of high-thr...
ICCAD
2008
IEEE
14 years 4 months ago
2008
IEEE
—We present in this paper a fast and stable global router called NTHU-Route 2.0 that improves the solution quality and runtime of a state-of-the-art router, NTHU-Route, by the fo...