436 search results - page 37 / 88 » Benchmarking and hardware implementation of JPEG-LS |
ISSS
2002
IEEE
14 years 2 months ago
2002
IEEE
Scheduling is widely recognized as a very important step in highlevel synthesis. Nevertheless, it is usually done without taking into account the effects on the actual hardware im...
ITC
1997
IEEE
14 years 1 months ago
1997
IEEE
This paper presents a new approach for designing test sequences to be generated on–chip. The proposed technique is based on machine learning, and provides a way to generate effi...
CAL
2006
13 years 9 months ago
2006
Hardware predictor designers have incorporated hysteresis and/or bias to achieve desired behavior by increasing the number of bits per counter. Some resulting proposed predictor de...
MICRO
2010
IEEE
13 years 7 months ago
2010
IEEE
Abstract--Adaptive microarchitectures are a promising solution for designing high-performance, power-efficient microprocessors. They offer the ability to tailor computational resou...
DSN
2007
IEEE
14 years 4 months ago
2007
IEEE
Synchronous circuits are typically clocked considering worst case timing paths so that timing errors are avoided under all circumstances. In the case of a pipelined processor, thi...