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ECOOP
2008
Springer
15 years 7 months ago
Online Phase-Adaptive Data Layout Selection
Good data layouts improve cache and TLB performance of object-oriented software, but unfortunately, selecting an optimal data layout a priori is NP-hard. This paper introduces layo...
Chengliang Zhang, Martin Hirzel
SASP
2009
IEEE
222views Hardware» more  SASP 2009»
16 years 15 days ago
A memory optimization technique for software-managed scratchpad memory in GPUs
—With the appearance of massively parallel and inexpensive platforms such as the G80 generation of NVIDIA GPUs, more real-life applications will be designed or ported to these pl...
Maryam Moazeni, Alex A. T. Bui, Majid Sarrafzadeh
FPL
2007
Springer
127views Hardware» more  FPL 2007»
15 years 12 months ago
Domain-Specific Hybrid FPGA: Architecture and Floating Point Applications
This paper presents a novel architecture for domain-specific FPGA devices. This architecture can be optimised for both speed and density by exploiting domain-specific informatio...
Chun Hok Ho, Chi Wai Yu, Philip Heng Wai Leong, Wa...
MICRO
2006
IEEE
155views Hardware» more  MICRO 2006»
15 years 11 months ago
In-Network Cache Coherence
With the trend towards increasing number of processor cores in future chip architectures, scalable directory-based protocols for maintaining cache coherence will be needed. Howeve...
Noel Eisley, Li-Shiuan Peh, Li Shang
DATE
2010
IEEE
105views Hardware» more  DATE 2010»
15 years 11 months ago
Modeling constructs and kernel for parallel simulation of accuracy adaptive TLMs
Abstract—We present a set of modeling constructs accompanied by a high performance simulation kernel for accuracy adaptive transaction level models. In contrast to traditional, ...
Rauf Salimi Khaligh, Martin Radetzki