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ASPDAC
1999
ACM
113views Hardware» more  ASPDAC 1999»
14 years 1 months ago
An Efficient Iterative Improvement Technique for VLSI Circuit Partitioning Using Hybrid Bucket Structures
In this paper, we present a fast and efficient Iterative Improvement Partitioning (IIP) technique for VLSI circuits and hybrid bucket structures on its implementation. Due to thei...
C. K. Eem, J. W. Chong
ISPD
1999
ACM
128views Hardware» more  ISPD 1999»
14 years 1 months ago
Transistor level micro-placement and routing for two-dimensional digital VLSI cell synthesis
There is an increasing need in modern VLSI designs for circuits implemented in high-performance logic families such as Cascode Voltage Switch Logic, Pass Transistor Logic, and dom...
Michael A. Riepe, Karem A. Sakallah
ICCAD
1997
IEEE
117views Hardware» more  ICCAD 1997»
14 years 1 months ago
Generalized matching from theory to application
This paper presents a novel approach for post-mapping optimization. We exploit the concept of generalized matching, a technique that nds symbolically all possible matching assignm...
Patrick Vuillod, Luca Benini, Giovanni De Micheli
ICCAD
1993
IEEE
104views Hardware» more  ICCAD 1993»
14 years 1 months ago
Parallel timing simulation on a distributed memory multiprocessor
Circuit simulation is one of the most computationally expensive tasks in circuit design and optimization. Detailed simulation at the level of precision of SPICE is usually perform...
Chih-Po Wen, Katherine A. Yelick
SIGMETRICS
1994
ACM
113views Hardware» more  SIGMETRICS 1994»
14 years 1 months ago
Shade: A Fast Instruction-Set Simulator for Execution Profiling
Shade is an instruction-set simulator and custom trace generator. Application programs are executed and traced under the control of a user-supplied trace analyzer. To reduce commu...
Robert F. Cmelik, David Keppel