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» Benchmarking and hardware implementation of JPEG-LS
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ISCA
2006
IEEE
133views Hardware» more  ISCA 2006»
14 years 1 months ago
TRAP-Array: A Disk Array Architecture Providing Timely Recovery to Any Point-in-time
RAID architectures have been used for more than two decades to recover data upon disk failures. Disk failure is just one of the many causes of damaged data. Data can be damaged by...
Qing Yang, Weijun Xiao, Jin Ren
CAV
2008
Springer
139views Hardware» more  CAV 2008»
13 years 9 months ago
CSIsat: Interpolation for LA+EUF
We present CSIsat, an interpolating decision procedure for the quantifier-free theory of rational linear arithmetic and equality with uninterpreted function symbols. Our implementa...
Dirk Beyer, Damien Zufferey, Rupak Majumdar
VLSID
2002
IEEE
177views VLSI» more  VLSID 2002»
14 years 8 months ago
RTL-Datapath Verification using Integer Linear Programming
Satisfiability of complex word-level formulas often arises as a problem in formal verification of hardware designs described at the register transfer level (RTL). Even though most...
Raik Brinkmann, Rolf Drechsler
ICCD
2005
IEEE
169views Hardware» more  ICCD 2005»
14 years 4 months ago
ALLCN: An Automatic Logic-to-Layout Tool for Carbon Nanotube Based Nanotechnology
— Since rapid progress has been made in device improvement and integration of small carbon nanotube fieldeffect transistors (CNFETs) circuits, the time has come for developing c...
Wei Zhang, Niraj K. Jha
ICCD
2002
IEEE
98views Hardware» more  ICCD 2002»
14 years 4 months ago
Parallel Multiple-Symbol Variable-Length Decoding
In this paper, a parallel Variable-Length Decoding (VLD) scheme is introduced. The scheme is capable of decoding all the codewords in an N-bit buffer whose accumulated codelength ...
Jari Nikara, Stamatis Vassiliadis, Jarmo Takala, M...