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» Bias and the limits of pooling
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GECCO
2004
Springer
14 years 1 months ago
High Temperature Experiments for Circuit Self-Recovery
Temperature and radiation tolerant electronics, as well as long life survivability are key capabilities required for future NASA missions. Current approaches to electronics for ext...
Didier Keymeulen, Ricardo Salem Zebulum, Vu Duong,...
ISLPED
2009
ACM
108views Hardware» more  ISLPED 2009»
14 years 1 months ago
Technology flavor selection and adaptive techniques for timing-constrained 45nm subthreshold circuits
We investigate techniques to design 45nm minimum-energy subthreshold CMOS circuits under timing constraints, considering the practical case of an 8-bit multiplier. We first show ...
David Bol, Denis Flandre, Jean-Didier Legat
AAAI
2008
13 years 10 months ago
Mathematical Modeling and Convergence Analysis of Trail Formation
An ant deposits pheromone along the path that it travels and is more likely to choose a path with a higher concentration of pheromone. The sensing and dropping of pheromone makes ...
Sameena Shah, Ravi Kothari, Jayadeva, Suresh Chand...
DAC
2005
ACM
13 years 10 months ago
Mapping statistical process variations toward circuit performance variability: an analytical modeling approach
A physical yet compact gate delay model is developed integrating short-channel effects and the Alpha-power law based timing model. This analytical approach accurately predicts bot...
Yu Cao, Lawrence T. Clark
ISLPED
2007
ACM
92views Hardware» more  ISLPED 2007»
13 years 10 months ago
Variable-latency adder (VL-adder): new arithmetic circuit design practice to overcome NBTI
Negative bias temperature instability (NBTI) has become a dominant reliability concern for nanoscale PMOS transistors. In this paper, we propose variable-latency adder (VL-adder) ...
Yiran Chen, Hai Li, Jing Li, Cheng-Kok Koh