9 search results - page 2 / 2 » Binding, Allocation and Floorplanning in Low Power High-Leve... |
DAC
1995
ACM
14 years 2 days ago
1995
ACM
This paper describes a technique for calculating the switching activity of a set of registers shared by di erent data values. Based on the assumption that the joint pdf (probabili...
TVLSI
2010
13 years 3 months ago
2010
In this paper, we present a low-power architectural synthesis system (LOPASS) for field-programmable gate-array (FPGA) designs with interconnect power estimation and optimization. ...
ISLPED
2003
ACM
14 years 1 months ago
2003
ACM
This paper addresses two aspects of low-power design for FPGA circuits. First, we present an RT-level power estimator for FPGAs with consideration of wire length. The power estima...
ISQED
2006
IEEE
14 years 2 months ago
2006
IEEE
As a result of aggressive technology scaling, gate leakage (gate oxide direct tunneling) has become a major component of total power dissipation. Use of dielectrics of higher perm...