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ICCD
2005
IEEE
124views Hardware» more  ICCD 2005»
14 years 4 months ago
A Thermally-Aware Methodology for Design-Specific Optimization of Supply and Threshold Voltages in Nanometer Scale ICs
As CMOS technology scales deeper into the nanometer regime, factors such as leakage power and chip temperature emerge as critically important concerns for VLSI design. This paper,...
Sheng-Chih Lin, Navin Srivastava, Kaustav Banerjee
DAC
2006
ACM
14 years 8 months ago
Gate sizing: finFETs vs 32nm bulk MOSFETs
FinFET devices promise to replace traditional MOSFETs because of superior ability in controlling leakage and minimizing short channel effects while delivering a strong drive curre...
Brian Swahn, Soha Hassoun
VLSID
2002
IEEE
122views VLSI» more  VLSID 2002»
14 years 8 months ago
Evaluating Run-Time Techniques for Leakage Power Reduction
While some leakage power reduction techniques require modification of process technology achieving savings at the fabrication stage, others are based on circuit-level optimization...
David Duarte, Yuh-Fang Tsai, Narayanan Vijaykrishn...
ASPDAC
2004
ACM
126views Hardware» more  ASPDAC 2004»
14 years 29 days ago
High-level area and power-up current estimation considering rich cell library
— Reducing the ever-growing leakage power is critical to power efficient designs. Leakage reduction techniques such as power-gating using sleep transistor insertion introduces la...
Fei Li, Lei He, Joseph M. Basile, Rakesh J. Patel,...
TVLSI
2008
126views more  TVLSI 2008»
13 years 7 months ago
Body Bias Voltage Computations for Process and Temperature Compensation
With continued scaling into the sub-90nm regime, the role of process, voltage and temperature (PVT) variations on the performance of VLSI circuits has become extremely important. T...
Sanjay V. Kumar, Chris H. Kim, Sachin S. Sapatneka...