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ICCD
1999
IEEE
122views Hardware» more  ICCD 1999»
14 years 28 days ago
Design and Evaluation of a Selective Compressed Memory System
This research explores any potential for an on-chip cache compression which can reduce not only cache miss ratio but also miss penalty, if main memory is also managed in compresse...
Jang-Soo Lee, Won-Kee Hong, Shin-Dug Kim
GLVLSI
2010
IEEE
164views VLSI» more  GLVLSI 2010»
14 years 1 months ago
Performance and energy trade-offs analysis of L2 on-chip cache architectures for embedded MPSoCs
On-chip memory organization is one of the most important aspects that can influence the overall system behavior in multiprocessor systems. Following the trend set by high-perform...
Mohamed M. Sabry, Martino Ruggiero, Pablo Garcia D...
MTDT
1999
IEEE
68views Hardware» more  MTDT 1999»
14 years 27 days ago
Unbalanced Cache Systems
The new concept of an unbalanced, hierarchicallydivided cache memory system is introduced and analyzed. This approach generalizes existing cache structures by allowing different m...
David L. Rhodes, Wayne Wolf
SAC
2009
ACM
14 years 3 months ago
Impact of NVRAM write cache for file system metadata on I/O performance in embedded systems
File systems make use of part of DRAM as the buffer cache to enhance its performance in traditional systems. In this paper, we consider the use of Non-Volatile RAM (NVRAM) as a w...
In Hwan Doh, Hyo J. Lee, Young Je Moon, Eunsam Kim...
DAC
2002
ACM
14 years 9 months ago
Schedulability of event-driven code blocks in real-time embedded systems
Many real-time embedded systems involve a collection of independently executing event-driven code blocks, having hard real-time constraints. Tasks in many such systems, like netwo...
Samarjit Chakraborty, Thomas Erlebach, Simon K&uum...