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ICCAD
2002
IEEE
176views Hardware» more  ICCAD 2002»
14 years 3 months ago
High capacity and automatic functional extraction tool for industrial VLSI circuit designs
In this paper we present an advanced functional extraction tool for automatic generation of high-level RTL from switch-level circuit netlist representation. The tool is called FEV...
Sasha Novakovsky, Shy Shyman, Ziyad Hanna
PLDI
2004
ACM
14 years 5 days ago
Jedd: a BDD-based relational extension of Java
In this paper we present Jedd, a language extension to Java that supports a convenient way of programming with Binary Decision Diagrams (BDDs). The Jedd language abstracts BDDs as...
Ondrej Lhoták, Laurie J. Hendren
CHI
2006
ACM
14 years 7 months ago
"Sketching" nurturing creativity: commonalities in art, design, engineering and research
icians or philosophers use abstract symbols to derive formulas or form proofs. Indeed, these sketches are structural geometric proofs, consistent with Plato's supposition that...
Kumiyo Nakakoji, Atau Tanaka, Daniel Fallman
DAC
2009
ACM
14 years 7 months ago
Timing-driven optimization using lookahead logic circuits
This paper describes a function-based timing-driven optimization technique for the synthesis of multi-level logic circuits. Motivated by the principles of parallel prefix computat...
Mihir R. Choudhury, Kartik Mohanram
DATE
2009
IEEE
113views Hardware» more  DATE 2009»
14 years 1 months ago
Exploiting structure in an AIG based QBF solver
—In this paper we present a procedure for solving quantified boolean formulas (QBF), which uses And-Inverter Graphs (AIGs) as the core data-structure. We make extensive use of s...
Florian Pigorsch, Christoph Scholl