46 search results - page 1 / 10 » Boolean Satisfiability and Equivalence Checking Using Genera... |
ICCD
1991
IEEE
13 years 11 months ago
1991
IEEE
ISQED
2002
IEEE
14 years 19 days ago
2002
IEEE
State-of-the-art verification tools are based on efficient operations on Boolean formulas. Traditional manipulation techniques are based on Binary Decision Diagrams (BDDs) and SAT...
DATE
2003
IEEE
14 years 1 months ago
2003
IEEE
: Binary Decision Diagrams (BDDs) have been widely used in synthesis and verification. Boolean Satisfiability (SAT) Solvers, on the other hand, have been gaining
CAV
2000
Springer
13 years 11 months ago
2000
Springer
In this paper we show how to do symbolic model checking using Boolean Expression Diagrams (BEDs), a non-canonical representation for Boolean formulas, instead of Binary Decision Di...
DATE
1999
IEEE
14 years 1 days ago
1999
IEEE
The problem of checking the equivalence of combinational circuits is of key significance in the verification of digital circuits. In recent years, several approaches have been pro...