135 search results - page 9 / 27 » Bounded Synthesis |
ISQED
2005
IEEE
14 years 29 days ago
2005
IEEE
Reliability decisions taken early in system design can bring significant benefits in terms of design quality. This paper presents a 0-1 integer linear programming (ILP) formulatio...
ICRA
2005
IEEE
14 years 29 days ago
2005
IEEE
— We explore the control synthesis problem for a robot dynamically manipulating an object in the presence of multiple frictional contacts. Contacts occur both between the object ...
DATE
2003
IEEE
14 years 20 days ago
2003
IEEE
We present a high-level synthesis algorithm solving the combined scheduling, allocation and binding problem minimizing area under both latency and maximum power per clock-cycle co...
FPGA
1995
ACM
13 years 11 months ago
1995
ACM
A novel approach is presented for transforming a given scheduled and bound signal processing algorithm for a multiplexer based datapath to a BUS/RAM based FPGA datapath. A datapat...
ICCAD
2010
IEEE
13 years 5 months ago
2010
IEEE
Craig Interpolation is a state-of-the-art technique for logic synthesis and verification, based on Boolean Satisfiability (SAT). Leveraging the efficacy of SAT algorithms, Craig In...