Abstract—Modeling parasitic parameters of Through-SiliconVia (TSV) structures is essential in exploring electrical characteristics such as delay and signal integrity (SI) of circ...
Roshan Weerasekera, Matt Grange, Dinesh Pamunuwa, ...
Abstract— With technology scaling, on-chip power densities are growing steadily, leading to the point where temperature has become an important consideration in the design of ele...
As semiconductor manufacturing requires greater capital investments, the use of contract foundries has grown dramatically, increasing exposure to mask theft and unauthorized exces...
In order to reduce the time-to-market and simplify gatelevel test generation for digital integrated circuits, GAbased functional test generation techniques are proposed for behavi...
A new algorithm is presented that combines performance and variation objectives in a behavioural model for a given analogue circuit topology and process. The tradeoffs between per...
Sawal Ali, Reuben Wilcock, Peter R. Wilson, Andrew...