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HPCA
2008
IEEE
14 years 8 months ago
Address-branch correlation: A novel locality for long-latency hard-to-predict branches
Hard-to-predict branches depending on longlatency cache-misses have been recognized as a major performance obstacle for modern microprocessors. With the widening speed gap between...
Hongliang Gao, Yi Ma, Martin Dimitrov, Huiyang Zho...
SBACPAD
2006
IEEE
147views Hardware» more  SBACPAD 2006»
14 years 1 months ago
Controlling the Power and Area of Neural Branch Predictors for Practical Implementation in High-Performance Processors
Neural-inspired branch predictors achieve very low branch misprediction rates. However, previously proposed implementations have a variety of characteristics that make them challe...
Daniel A. Jiménez, Gabriel H. Loh
ASPLOS
2009
ACM
14 years 8 months ago
Phantom-BTB: a virtualized branch target buffer design
Modern processors use branch target buffers (BTBs) to predict the target address of branches such that they can fetch ahead in the instruction stream increasing concurrency and pe...
Ioana Burcea, Andreas Moshovos
ISCAPDCS
2003
13 years 9 months ago
N-Tuple Compression: A Novel Method for Compression of Branch Instruction Traces
Branch predictors and processor front-ends have been the focus of a number of computer architecture studies. Typically they are evaluated separately from other components using tr...
Aleksandar Milenkovic, Milena Milenkovic, Jeffrey ...
CORR
2006
Springer
109views Education» more  CORR 2006»
13 years 7 months ago
On Conditional Branches in Optimal Decision Trees
The decision tree is one of the most fundamental ing abstractions. A commonly used type of decision tree is the alphabetic binary tree, which uses (without loss of generality) &quo...
Michael B. Baer