21 search results - page 4 / 5 » Buffer Insertion Considering Process Variation |
GLVLSI
2009
IEEE
14 years 2 months ago
2009
IEEE
Clock distribution networks are an important design issue that is highly dependent on delay variations and load imbalances, while requiring power efficiency. Existing mesh solutio...
ASPDAC
2008
ACM
13 years 9 months ago
2008
ACM
This paper investigates methods for minimizing the impact of process variation on clock skew using buffer and wire sizing. While most papers on clock trees ignore data-path circuit...
ASPDAC
2010
ACM
13 years 5 months ago
2010
ACM
Abstract--In nanometer-scale VLSI physical design, clock network becomes a major concern on determining the total performance of digital circuit. Clock skew and PVT (Process, Volta...
JEI
2002
13 years 7 months ago
2002
The recent proliferation of digital multimedia content has raised concerns about authentication mechanisms for multimedia data. A number of authentication techniques based on digi...
ISQED
2002
IEEE
14 years 10 days ago
2002
IEEE
As the process technology advances into the deep submicron era, interconnect plays a dominant role in determining circuit performance. Buffer insertion/sizing and wire sizing are ...