37 search results - page 3 / 8 » Buffer Insertion for Noise and Delay Optimization |
DAC
2003
ACM
14 years 9 months ago
2003
ACM
The classic algorithm for optimal buffer insertion due to van Ginneken has time and space complexity O(n2 ), where n is the number of possible buffer positions. We present a new a...
ASPDAC
2006
ACM
14 years 2 months ago
2006
ACM
— Buffer insertion is an effective technique to reduce interconnect delay. In this paper, we give a simple O(mn) time algorithm for optimal buffer insertion, where m is the numbe...
ISCAS
2005
IEEE
14 years 2 months ago
2005
IEEE
-- Timing optimization is an important goal of global routing in deep submicron era. To guarantee the timing performance of the circuit, merely adopting topology optimization becom...
DAC
2005
ACM
14 years 9 months ago
2005
ACM
This paper presents the first in-depth study on applying dual Vdd buffers to buffer insertion and multi-sink buffered tree construction for power minimization under delay constrai...
TVLSI
2010
13 years 3 months ago
2010
A new approach for resource based optimization for high performance integrated circuits is presented. The methodology is applied to simultaneous shield and repeater insertion, resu...