69 search results - page 12 / 14 » Buffer insertion for clock delay and skew minimization |
EMSOFT
2005
Springer
14 years 1 months ago
2005
Springer
We propose a programming model dedicated to real-time videostreaming applications for embedded media devices, including highdefinition TVs. This model is built on the synchronous...
ASPDAC
2005
ACM
13 years 9 months ago
2005
ACM
In modern VLSI designs, the increasingly severe power problem requests to minimize clock routing wirelength so that both power consumption and power supply noise can be alleviated...
PODC
2009
ACM
14 years 8 months ago
2009
ACM
d Abstract] Christoph Lenzen Computer Engineering and Networks Laboratory (TIK) ETH Zurich, 8092 Zurich, Switzerland lenzen@tik.ee.ethz.ch Thomas Locher Computer Engineering and N...
ISLPED
2007
ACM
13 years 9 months ago
2007
ACM
This paper addresses the problem of power-optimal repeater insertion for global buses in the presence of crosstalk noise. MTCMOS technique by inserting high-Vth sleep transistors ...
ISLPED
1996
ACM
13 years 12 months ago
1996
ACM
In this paper, we study the simultaneous buffer and wire sizing (SBWS) problem for delay and power dissipation minimization. We prove the BS/WS relation for optimal SBWS solutions...