69 search results - page 8 / 14 » Buffer insertion for clock delay and skew minimization |
ASPDAC
1995
ACM
13 years 11 months ago
1995
ACM
A heuristic algorithm for a given topology of a multiple-source and multiple-sink bus to reduce the signal delay time is proposed. The algorithm minimizes the delay by inserting bu...
ASPDAC
2005
ACM
14 years 1 months ago
2005
ACM
: In ultra-deep submicron VLSI circuits, clock network is a major source of power consumption and power supply noise. Therefore, it is very important to minimize clock network size...
ICCAD
1999
IEEE
14 years 4 days ago
1999
IEEE
This paper studies buffer block planning for interconnect-driven floorplanning in deep submicron designs. We first introduce the concept of feasible region (FR) for buffer inserti...
ISCAS
2007
IEEE
14 years 2 months ago
2007
IEEE
— A methodology based on supply voltage optimization for lowering the power consumption and temperature fluctuations induced skew of clock distribution networks is proposed in th...
ICCAD
2004
IEEE
14 years 4 months ago
2004
IEEE
Traditional timing-driven placement considers only combinational delays and does not take into account the potential of subsequent sequential optimization steps. As a result, the ...