92 search results - page 8 / 19 » Building heterogeneous reconfigurable systems with a hardwar... |
150
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IJCAI
1997
15 years 7 months ago
1997
This paper describes an evolvable hardware (EHW) system for generalized neural network learning. We have developed an ASIC VLSI chip, which is a building block to configure a scal...
151
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FPL
2007
Springer
15 years 7 months ago
2007
Springer
Reconfiguration time in dynamically-reconfigurable modular systems can severely limit application run-time compared to the critical path delay. In this paper we present a novel ...
141
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FPL
2005
Springer
15 years 11 months ago
2005
Springer
Due to their layered approach, Networks-on-Chip (NoC) are a promising communication backbone in the field of heterogeneous dynamically reconfigurable systems. In this paper a fu...
176
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ERSA
2007
15 years 7 months ago
2007
- Even though state-of-the-art FPGAs present new opportunities in exploring low-cost high-performance architectures for floating-point scientific applications, they also pose serio...
133
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DATE
2010
IEEE
15 years 10 months ago
2010
IEEE
—In this paper, we present a method to analyze different implementations of stream-based applications on heterogeneous multiprocessor systems. We take both resource usage and per...