Sciweavers

426 search results - page 15 / 86
» Building the functional performance model of a processor
Sort
View
JUCS
2000
120views more  JUCS 2000»
13 years 8 months ago
Execution and Cache Performance of the Scheduled Dataflow Architecture
: This paper presents an evaluation of our Scheduled Dataflow (SDF) Processor. Recent focus in the field of new processor architectures is mainly on VLIW (e.g. IA-64), superscalar ...
Krishna M. Kavi, Joseph Arul, Roberto Giorgi
DATE
2003
IEEE
117views Hardware» more  DATE 2003»
14 years 1 months ago
Exploring SW Performance Using SoC Transaction-Level Modeling
This paper presents VISTA, a new methodology and tool dedicated to analyse system level performance by executing full-scale SW application code on a transaction-level model of the...
Imed Moussa, Thierry Grellier, Giang Nguyen
HPDC
2002
IEEE
14 years 1 months ago
Using Kernel Couplings to Predict Parallel Application Performance
Performance models provide significant insight into the performance relationships between an application and the system used for execution. The major obstacle to developing perfor...
Valerie E. Taylor, Xingfu Wu, Jonathan Geisler, Ri...
MICRO
2002
IEEE
124views Hardware» more  MICRO 2002»
14 years 1 months ago
Optimizing pipelines for power and performance
During the concept phase and definition of next generation high-end processors, power and performance will need to be weighted appropriately to deliver competitive cost/performan...
Viji Srinivasan, David Brooks, Michael Gschwind, P...
ISLPED
2007
ACM
169views Hardware» more  ISLPED 2007»
13 years 10 months ago
Throughput of multi-core processors under thermal constraints
We analyze the effect of thermal constraints on the performance and power of multi-core processors. We propose system-level power and thermal models, and derive expressions for (a...
Ravishankar Rao, Sarma B. K. Vrudhula, Chaitali Ch...