416 search results - page 78 / 84 » CMOL FPGA circuits |
GLVLSI
2006
IEEE
14 years 3 months ago
2006
IEEE
This paper presents a minimum area, low-power driven clustering algorithm for coarse-grained, antifuse-based FPGAs under delay constraints. The algorithm accurately predicts logic...
ICRA
2006
IEEE
14 years 3 months ago
2006
IEEE
— This paper describes a 1,000Hz visual feedback using the CMOS+FPGA vision. It is required to obtain positional and angular signals around 1,000Hz to control a mechanical system...
IPPS
2006
IEEE
14 years 3 months ago
2006
IEEE
The development of Field Programmable Gate Arrays (FPGAs) had tremendous improvements in the last few years. They were extended from simple logic circuits to complex Systems-on-Ch...
IPPS
2006
IEEE
14 years 3 months ago
2006
IEEE
Digital Down Conversion (DDC) is an algorithm, used to lower the amount of samples per second by selecting a limited frequency band out of a stream of samples. A possible DDC algo...
DATE
2005
IEEE
14 years 3 months ago
2005
IEEE
Visual information processing will play an increasingly important role in future electronics systems. In many applications, e.g. video surveillance cameras, data throughput of mic...