9 search results - page 2 / 2 » CMOS Circuit Design for Minimum Dynamic Power and Highest Sp... |
ICCD
2001
IEEE
14 years 3 months ago
2001
IEEE
Dynamic power is the main source of power consumption in CMOS circuits. It depends on the square of the supply voltage. It may significantly be reduced by scaling down the supply ...
ISCAS
1999
IEEE
13 years 11 months ago
1999
IEEE
- A closed form expression for the propagation delay of a CMOS gate driving a distributed RLC line is introduced that is within 5% of dynamic circuit simulations for a wide range o...
ISLPED
2009
ACM
14 years 1 months ago
2009
ACM
In this paper, we observe that minimum energy Emin of subthreshold logic dramatically increases when reaching 45 nm node. We demonstrate by circuit simulation and analytical model...
VLSID
2007
IEEE
14 years 7 months ago
2007
IEEE
In the past, Field Programmable Gate Array (FPGA) circuits only contained a limited amount of logic and operated at a low frequency. Few applications running on FPGAs consumed exc...