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AHS
2006
IEEE
95views Hardware» more  AHS 2006»
13 years 11 months ago
A Modular Framework for the Evolution of Circuits on Configurable Transistor Array Architectures
This paper gives an overview over the progress that has been made by the Heidelberg FPTA group within the field of analog evolvable hardware. Achievements are the design of a CMOS...
Martin Trefzer, Jörg Langeheine, Karlheinz Me...
ASPDAC
2004
ACM
79views Hardware» more  ASPDAC 2004»
13 years 11 months ago
NSGA-based parasitic-aware optimization of a 5GHz low-noise VCO
Abstract--A parasitic-aware RF synthesis tool based on a nondominated sorting genetic algorithm (NSGA) is introduced. The NSGA-based optimizer casts the design problem as a multi-o...
Min Chu, David J. Allstot, Jeffrey M. Huard, Kim Y...
DATE
2005
IEEE
120views Hardware» more  DATE 2005»
13 years 9 months ago
Simulation Methodology for Analysis of Substrate Noise Impact on Analog / RF Circuits Including Interconnect Resistance
This paper reports a novel simulation methodology for analysis and prediction of substrate noise impact on analog / RF circuits taking into account the role of the parasitic resis...
Charlotte Soens, Geert Van der Plas, Piet Wambacq,...
NOCS
2009
IEEE
14 years 2 months ago
A GALS many-core heterogeneous DSP platform with source-synchronous on-chip interconnection network
This paper presents a many-core heterogeneous computational platform that employs a GALS compatible circuit-switched on-chip network. The platform targets streaming DSP and embedd...
Anh T. Tran, Dean Truong, Bevan M. Baas
ISLPED
2009
ACM
168views Hardware» more  ISLPED 2009»
14 years 2 months ago
Low power circuit design based on heterojunction tunneling transistors (HETTs)
The theoretical lower limit of subthreshold swing in MOSFETs (60 mV/decade) significantly restricts low voltage operation since it results in a low ON to OFF current ratio at low ...
Daeyeon Kim, Yoonmyung Lee, Jin Cai, Isaac Lauer, ...