A gated current-controlled oscillator (GCCO) based topology is used to implement a low-power multi-channel clock and data recovery (CDR) system in a 0.18um digital CMOS technology...
Armin Tajalli, Paul Muller, Seyed Mojtaba Atarodi,...
—A low-latency, HDL-synthesizable dynamic clock frequency controller is presented as a time-efficient alternative to full-custom implementations. Frequency division of a fully in...
Robert M. Senger, Eric D. Marsman, Gordy A. Carich...
Abstract— It is important to separate random jitter from deterministic jitter to quantify their contributions to the total jitter. This paper identifies the limitations of the e...
—A digitally-calibrated technique to suppress the supply voltage sensitivity of a phase-locked loop (PLL) is presented. The voltage-controlled ring oscillator with an additional ...
The purpose of this work is to explore how device operation parameters such as switching speed and power dissipation scale with voltage and temperature. We simulated a CMOS ring o...