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ISLPED
2005
ACM
96views Hardware» more  ISLPED 2005»
14 years 1 months ago
A low-power, multichannel gated oscillator-based CDR for short-haul applications
A gated current-controlled oscillator (GCCO) based topology is used to implement a low-power multi-channel clock and data recovery (CDR) system in a 0.18um digital CMOS technology...
Armin Tajalli, Paul Muller, Seyed Mojtaba Atarodi,...
ISCAS
2006
IEEE
95views Hardware» more  ISCAS 2006»
14 years 1 months ago
Low-latency, HDL-synthesizable dynamic clock frequency controller with self-referenced hybrid clocking
—A low-latency, HDL-synthesizable dynamic clock frequency controller is presented as a time-efficient alternative to full-custom implementations. Frequency division of a fully in...
Robert M. Senger, Eric D. Marsman, Gordy A. Carich...
ASPDAC
2006
ACM
107views Hardware» more  ASPDAC 2006»
14 years 1 months ago
Jitter decomposition in ring oscillators
Abstract— It is important to separate random jitter from deterministic jitter to quantify their contributions to the total jitter. This paper identifies the limitations of the e...
Qingqi Dou, Jacob A. Abraham
TVLSI
2011
343views more  TVLSI 2011»
13 years 2 months ago
A Digitally-Calibrated Phase-Locked Loop With Supply Sensitivity Suppression
—A digitally-calibrated technique to suppress the supply voltage sensitivity of a phase-locked loop (PLL) is presented. The voltage-controlled ring oscillator with an additional ...
Shih-Yuan Kao, Shen-Iuan Liu
ISQED
2005
IEEE
95views Hardware» more  ISQED 2005»
14 years 1 months ago
Simulating and Improving Microelectronic Device Reliability by Scaling Voltage and Temperature
The purpose of this work is to explore how device operation parameters such as switching speed and power dissipation scale with voltage and temperature. We simulated a CMOS ring o...
Xiaojun Li, Joerg D. Walter, Joseph B. Bernstein