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ISCAS
2005
IEEE
181views Hardware» more  ISCAS 2005»
14 years 1 months ago
Wide frequency range voltage controlled ring oscillators based on transmission gates
In this paper, a voltage-controlled ring oscillator (VCO) with wide linear tuning frequency range capability based on transmission gates is described. It also features the rapid v...
Meng-Lieh Sheu, Ta-Wei Lin, Wei-Hung Hsu
ICCD
2001
IEEE
88views Hardware» more  ICCD 2001»
14 years 4 months ago
Jitter-Induced Power/ground Noise in CMOS PLLs: A Design Perspective
CMOS Phase-locked loops (PLL) are ubiquitous in RF and mixed-signal integrated circuits. PLLs are very sensitive to noise fluctuations on the power and ground rails. In this paper...
Payam Heydari, Massoud Pedram
ISCAS
2008
IEEE
134views Hardware» more  ISCAS 2008»
14 years 2 months ago
A 25MHz all-CMOS reference clock generator for XO-replacement in serial wire interfaces
—A 25MHz all-CMOS clock generator is demonstrated where measured performance makes it suitable for direct replacement of the reference crystal oscillator (XO) for serial wire int...
Michael S. McCorquodale, Scott M. Pernia, Sundus K...
ICONIP
2007
13 years 9 months ago
Analog CMOS Circuits Implementing Neural Segmentation Model Based on Symmetric STDP Learning
We proposed a neural segmentation model that is suitable for implementation in analog VLSIs using conventional CMOS technology. The model consists of neural oscillators mutually co...
Gessyca Maria Tovar, Eric Shun Fukuda, Tetsuya Asa...
DDECS
2009
IEEE
111views Hardware» more  DDECS 2009»
14 years 2 months ago
0.5V 160-MHz 260uW all digital phase-locked loop
– A low power all-digital phase locked-loop (ADPLL) in a 0.13um CMOS process is presented. The pulse-based digitally controlled oscillator (PB-DCO) performs a high resolution and...
Jen-Chieh Liu, Hong-Yi Huang, Wei-Bin Yang, Kuo-Hs...