869 search results - page 101 / 174 » Cache Architectures for Reconfigurable Hardware |
PDP
2010
IEEE
14 years 6 hour ago
2010
IEEE
In the last years high performance processor designs have evolved toward Chip-Multiprocessor (CMP) architectures that implement multiple processing cores on a single die. As the nu...
MICRO
1994
IEEE
13 years 11 months ago
1994
IEEE
Multiple issue of instructions occurs in superscalar and VLIW machines. This paper investigates a third type of machine design, which combines the advantages of code compatibility...
CLUSTER
2008
IEEE
14 years 2 months ago
2008
IEEE
—User-level communication allows an application process to access the network interface directly. Bypassing the kernel requires that a user process accesses the network interface...
DAC
2010
ACM
13 years 8 months ago
2010
ACM
This paper describes a fast, automated technique for accurate on-line estimation of the performance and power consumption of interacting processes in a multi-programmed, multi-cor...
SIGMETRICS
1997
ACM
13 years 12 months ago
1997
ACM
In this paper we present a performance study of memory reference behavior in network protocol processing, using an Internet-based protocol stack implemented in the x-kernel runnin...