869 search results - page 117 / 174 » Cache Architectures for Reconfigurable Hardware |
WMPI
2004
ACM
14 years 1 months ago
2004
ACM
The size and speed of first-level caches and SRAMs of embedded processors continue to increase in response to demands for higher performance. In power-sensitive devices like PDAs a...
MICRO
2007
IEEE
14 years 1 months ago
2007
IEEE
A significant part of future microprocessor real estate will be dedicated to L2 or L3 caches. These on-chip caches will heavily impact processor performance, power dissipation, a...
ANCS
2010
ACM
13 years 5 months ago
2010
ACM
As we move forward towards the next generation of wireless protocols, the push for a better radio physical layer is ever increasing. Conventional radio architectures are limited t...
ISCA
2009
IEEE
14 years 2 months ago
2009
IEEE
This paper presents a novel technique, Memory Mapped ECC, which reduces the cost of providing error correction for SRAM caches. It is important to limit such overheads as processo...
DATE
2009
IEEE
14 years 2 months ago
2009
IEEE
—As semiconductor manufacturing enters advanced nanometer design paradigm, aging and device wear-out related degradation is becoming a major concern. Negative Bias Temperature In...