869 search results - page 141 / 174 » Cache Architectures for Reconfigurable Hardware |
MICRO
2003
IEEE
14 years 25 days ago
2003
IEEE
Abstract—High-speed routers often use commodity, fully-associative, TCAMs (Ternary Content Addressable Memories) to perform packet classification and routing (IP lookup). We prop...
ICCD
2006
IEEE
14 years 4 months ago
2006
IEEE
— Caches, block memories, predictors, state tables, and other forms of on-chip memory are continuing to consume a greater portion of processor designs with each passing year. Mak...
ISCA
2002
IEEE
14 years 14 days ago
2002
IEEE
Tarantula is an aggressive floating point machine targeted at technical, scientific and bioinformatics workloads, originally planned as a follow-on candidate to the EV8 processo...
ISCA
2003
IEEE
14 years 25 days ago
2003
IEEE
Meeting deadlines is a key requirement in safe realtime systems. Worst-case execution times (WCET) of tasks are needed for safe planning. Contemporary worst-case timing analysis t...
ISCA
2000
IEEE
13 years 12 months ago
2000
IEEE
The register file access time is one of the critical delays in current superscalar processors. Its impact on processor performance is likely to increase in future processor genera...