869 search results - page 73 / 174 » Cache Architectures for Reconfigurable Hardware |
FCCM
2008
IEEE
14 years 5 months ago
2008
IEEE
Although pipelining or C-slowing an FPGA-based application can potentially dramatically improve the performance, this poses a question for conventional reconfigurable architecture...
DATE
1999
IEEE
14 years 3 months ago
1999
IEEE
This paper proposes a methodology to evaluate the effects of encodings on the power consumption of system-level buses in the presence of multi-level cache memories. The proposed m...
MICRO
2010
IEEE
13 years 9 months ago
2010
IEEE
We propose an architectural design methodology for designing formally verifiable cache coherence protocols, called Fractal Coherence. Properly designed to be fractal in behavior, t...
ISCAS
2006
IEEE
14 years 5 months ago
2006
IEEE
Abstract— Shared memory is a common inter-processor communication paradigm for on-chip multiprocessor SoC (MPSoC) platforms. The latency overhead of switch-based interconnection ...
ECOOP
2008
Springer
14 years 29 days ago
2008
Springer
Abstract. The paradigm shift in processor design from monolithic processors to multicore has renewed interest in programming models that facilitate parallelism. While multicores ar...