869 search results - page 87 / 174 » Cache Architectures for Reconfigurable Hardware |
IEEEPACT
2009
IEEE
14 years 3 months ago
2009
IEEE
—Bulk memory copying and initialization is one of the most ubiquitous operations performed in current computer systems by both user applications and Operating Systems. While many...
ARC
2006
Springer
14 years 21 days ago
2006
Springer
We introduce a new paradigm in the computer architecture referred to as Polymorphic Instruction Set Computers (PISC). This new paradigm, in difference to RISC/CISC, introduces hard...
ASPDAC
2007
ACM
14 years 29 days ago
2007
ACM
Turbo decoding architectures have greater error correcting capability than any other known code. Due to their excellent performance turbo codes have been employed in several trans...
MSE
2002
IEEE
14 years 1 months ago
2002
IEEE
This paper presents the study of running several core multimedia applications on a simultaneous multithreading (SMT) architecture and derives design principles for multimedia soft...
DAC
2008
ACM
14 years 10 months ago
2008
ACM
We present a cross-layer customization methodology for latency and bandwidth efficient inter-core communication in embedded multiprocessors. The methodology integrates compiler, o...