869 search results - page 89 / 174 » Cache Architectures for Reconfigurable Hardware |
FPL
2005
Springer
14 years 2 months ago
2005
Springer
Due to their layered approach, Networks-on-Chip (NoC) are a promising communication backbone in the field of heterogeneous dynamically reconfigurable systems. In this paper a fu...
DATE
2008
IEEE
14 years 3 months ago
2008
IEEE
Functional, instruction-based self-testing of microprocessors has recently emerged as an effective alternative or supplement to other testing approaches, and is progressively adop...
SBCCI
2006
ACM
14 years 2 months ago
2006
ACM
Platform-based design is a method to implement complex SoCs, avoiding chip design from scratch. A promising evolution of platform-based design are MPSoC. Such generic architecture...
ISCA
2010
IEEE
13 years 11 months ago
2010
IEEE
This paper explores the design space of MMU caches that accelerate virtual-to-physical address translation in processor architectures, such as x86-64, that use a radix tree page t...
ASAP
2006
IEEE
13 years 11 months ago
2006
IEEE
Several semi-parallel decoding architectures have been explored by researchers for the quasi-cyclic low density parity check (LDPC) codes. In these architectures, the reconfigurab...