Sciweavers

520 search results - page 27 / 104
» Cache Post-Relational Technology
Sort
View
DATE
2009
IEEE
132views Hardware» more  DATE 2009»
14 years 5 months ago
Power and performance of read-write aware Hybrid Caches with non-volatile memories
—Caches made of non-volatile memory technologies, such as Magnetic RAM (MRAM) and Phase-change RAM (PRAM), offer dramatically different power-performance characteristics when com...
Xiaoxia Wu, Jian Li, Lixin Zhang, Evan Speight, Yu...
DAC
2002
ACM
14 years 12 months ago
DRG-cache: a data retention gated-ground cache for low power
In this paper we propose a novel integrated circuit and architectural level technique to reduce leakage power consumption in high performance cache memories using single Vt (trans...
Amit Agarwal, Hai Li, Kaushik Roy
CIKM
2009
Springer
14 years 5 months ago
Location cache for web queries
This paper proposes a strategy to reduce the amount of hardware involved in the solution of search engine queries. It proposes using a secondary compact cache that keeps minimal i...
Mauricio Marín, Flavio Ferrarotti, Marcelo ...
DATE
2003
IEEE
84views Hardware» more  DATE 2003»
14 years 4 months ago
PARLAK: Parametrized Lock Cache Generator
A system-on-chip lock cache (SoCLC) is an intellectual property (IP) core that provides effective lock synchronization in a heterogeneous multiprocessor shared-memory system-on-ac...
Bilge Saglam Akgul, Vincent John Mooney III
TVLSI
2008
89views more  TVLSI 2008»
13 years 10 months ago
Test Set Development for Cache Memory in Modern Microprocessors
Up to 53% of the time spent on testing current Intel microprocessors is needed to test on-chip caches, due to the high complexity of memory tests and to the large amount of transis...
Zaid Al-Ars, Said Hamdioui, Georgi Gaydadjiev, Sta...