Sciweavers

39 search results - page 4 / 8
» Caching all plans with just one optimizer call
Sort
View
ISCA
2005
IEEE
117views Hardware» more  ISCA 2005»
14 years 21 days ago
Store Vulnerability Window (SVW): Re-Execution Filtering for Enhanced Load Optimization
The load-store unit is a performance critical component of a dynamically-scheduled processor. It is also a complex and non-scalable component. Several recently proposed techniques...
Amir Roth
FOCS
2008
IEEE
14 years 1 months ago
Kakeya Sets, New Mergers and Old Extractors
A merger is a probabilistic procedure which extracts the randomness out of any (arbitrarily correlated) set of random variables, as long as one of them is uniform. Our main result...
Zeev Dvir, Avi Wigderson
ICCD
2006
IEEE
117views Hardware» more  ICCD 2006»
14 years 4 months ago
Fast, Performance-Optimized Partial Match Address Compression for Low-Latency On-Chip Address Buses
— The influence of interconnects on processor performance and cost is becoming increasingly pronounced with technology scaling. In this paper, we present a fast compression sche...
Jiangjiang Liu, Krishnan Sundaresan, Nihar R. Maha...
SIGMOD
2008
ACM
145views Database» more  SIGMOD 2008»
14 years 7 months ago
Optimizing complex queries with multiple relation instances
Today's query processing engines do not take advantage of the multiple occurrences of a relation in a query to improve performance. Instead, each instance is treated as a dis...
Yu Cao, Gopal C. Das, Chee Yong Chan, Kian-Lee Tan
SIGMETRICS
2005
ACM
120views Hardware» more  SIGMETRICS 2005»
14 years 20 days ago
Automatic measurement of memory hierarchy parameters
The running time of many applications is dominated by the cost of memory operations. To optimize such applications for a given platform, it is necessary to have a detailed knowled...
Kamen Yotov, Keshav Pingali, Paul Stodghill