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ISCAS
2007
IEEE

93views Hardware» more ISCAS 2007»

VLSI Implementation of a Lattice-Reduction Algorithm for Multi-Antenna Broadcast Precoding

14 years 4 months ago

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Abstract— This paper describes the ﬁrst VLSI implementation of lattice reduction (LR) aided multi-antenna broadcast precoding with vector perturbation. The considered LR scheme...

Andreas Burg, Dominik Seethaler, Gerald Matz

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ICES
2003
Springer

165views Hardware» more ICES 2003»

Speeding up Hardware Evolution: A Coprocessor for Evolutionary Algorithms

14 years 3 months ago

Download www.kip.uni-heidelberg.de

This paper proposes a coprocessor architecture to speed up hardware evolution. It is designed to be implemented in an FPGA with an integrated microprocessor core. The coprocessor r...

Tillmann Schmitz, Steffen G. Hohmann, Karlheinz Me...

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COGSR
2011

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Rethinking cognitive architecture via graphical models

13 years 5 months ago

Download www-bcf.usc.edu

Cognitive architectures need to resolve the diversity dilemma – i.e., to blend diversity and simplicity – in order to couple functionality and efficiency with integrability, e...

Paul S. Rosenbloom

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DAC
1992
ACM

82views Computer Architecture» more DAC 1992»

On the Over-Specification Problem in Sequential ATPG Algorithms

14 years 2 months ago