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DATE
2000
IEEE
137views Hardware» more  DATE 2000»
14 years 1 months ago
Retargeting of Compiled Simulators for Digital Signal Processors Using a Machine Description Language
This paper presents a methodology to retarget the technique of compiled simulation for Digital Signal Processors DSPs using the modeling language LISA. In the past, the principl...
Stefan Pees, Andreas Hoffmann, Heinrich Meyr
ICFCA
2007
Springer
14 years 28 days ago
Performances of Galois Sub-hierarchy-building Algorithms
Abstract. The Galois Sub-hierarchy (GSH) is a polynomial-size representation of a concept lattice which has been applied to several fields, such as software engineering and linguis...
Gabriela Arévalo, Anne Berry, Marianne Huch...
DAC
2000
ACM
14 years 10 months ago
Designing systems-on-chip using cores
Leading-edge systems-on-chip (SoC) being designed today could reach 20 Million gates and 0.5 to 1 GHz operating frequency. In order to implement such systems, designers are increa...
Reinaldo A. Bergamaschi, William R. Lee
TEC
2008
100views more  TEC 2008»
13 years 9 months ago
Real-Valued Compact Genetic Algorithms for Embedded Microcontroller Optimization
Recent research on compact genetic algorithms (cGAs) has proposed a number of evolutionary search methods with reduced memory requirements. In cGAs, the evolution of populations is...
Ernesto Mininno, Francesco Cupertino, David Naso
SIGMETRICS
2011
ACM
196views Hardware» more  SIGMETRICS 2011»
13 years 4 months ago
Performance analysis of the OP2 framework on many-core architectures
We present a performance analysis and benchmarking study P2 “active” library, which provides an abstraction framework for the solution of parallel unstructured mesh applicatio...
M. B. Giles, Gihan R. Mudalige, Z. Sharif, Graham ...