In this paper, we study the simultaneous transistor and interconnect sizing (STIS) problem. We dene a class of optimization problems as CH-posynomial programs and reveal a genera...
—1 In this paper we present a stochastic model order reduction technique for interconnect extraction in the presence of process variabilities, i.e. variation-aware extraction. It...
Switch-setting games like Lights Out are typically modelled as a graph, where the vertices represent switches and lamps, and the edges capture the switching rules. We generalize t...
Let G = (V, E) be a graph. A set S V is a restrained dominating set if every vertex not in S is adjacent to a vertex in S and to a vertex in V - S. The restrained domination numb...
In this paper a new approach to solve constrained multi-objective problems by way of evolutionary multi-objective optimization is introduced. In contrast to former evolutionary ap...