An efficient approach to simultaneous transistor and interconnect sizing

In this paper, we study the simultaneous transistor and interconnect sizing (STIS) problem. We dene a class of optimization problems as CH-posynomial programs and reveal a general dominance property for all CH-posynomial programs (Theorem 1). We show that the STIS problems under a number of transistor delay models are CH-posynomial programs and propose an ecient and near-optimal STIS algorithm based on the dominance property. When used to solve the simultaneous driver/buer and wire sizing problem for real designs, it reduces the maximum delay by up to 16.1%, and more signicantly, reduces the power consump

• Type: Conference
• Year: 1996
• Where: ICCAD
• Authors: Jason Cong, Lei He
• Keywords: CH-posynomial Programs, Dominance Property, Hardware, ICCAD 1996, Near-optimal Stis Algorithm