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IPPS
2002
IEEE
15 years 7 months ago
Fast Inductance Extraction of Large VLSI Circuits
Accurate estimation of signal delay is critical to the design and verification of VLSI circuits. At very high frequencies, signal delay in circuits with small feature sizes is do...
Hemant Mahawar, Vivek Sarin, Weiping Shi
117
Voted
ICCAD
2000
IEEE
88views Hardware» more  ICCAD 2000»
15 years 7 months ago
Hierarchical Interconnect Circuit Models
The increasing size of integrated systems combined with deep submicron physical modeling details creates an explosion in RLC interconnect modeling complexity of unmanageable propo...
Michael W. Beattie, Satrajit Gupta, Lawrence T. Pi...
125
Voted
MST
2007
138views more  MST 2007»
15 years 2 months ago
Parameterized Complexity of Vertex Cover Variants
Important variants of the Vertex Cover problem (among others, Connected Vertex Cover, Capacitated Vertex Cover, and Maximum Partial Vertex Cover) have been intensively studied in ...
Jiong Guo, Rolf Niedermeier, Sebastian Wernicke
124
Voted
ICCAD
1999
IEEE
88views Hardware» more  ICCAD 1999»
15 years 7 months ago
Performance optimization under rise and fall parameters
Typically,cell parameterssuch as the pin-to-pinintrinsicdelays, load-dependentcoe cients,andinputpin capacitanceshavedifferent values for rising and falling signals. The performan...
Rajeev Murgai
96
Voted
DAC
1999
ACM
15 years 7 months ago
IC Analyses Including Extracted Inductance Models
IC inductance extraction generally produces either port inductances based on simplified current path assumptions or a complete partial inductance matrix. Combining either of thes...
Michael W. Beattie, Lawrence T. Pileggi