Sciweavers

1333 search results - page 178 / 267
» Categorial Minimalism
Sort
View
CASES
2009
ACM
14 years 15 days ago
A fault tolerant cache architecture for sub 500mV operation: resizable data composer cache (RDC-cache)
In this paper we introduce Resizable Data Composer-Cache (RDC-Cache). This novel cache architecture operates correctly at sub 500 mV in 65 nm technology tolerating large number of...
Avesta Sasan, Houman Homayoun, Ahmed M. Eltawil, F...
CODES
2005
IEEE
14 years 2 months ago
Aggregating processor free time for energy reduction
Even after carefully tuning the memory characteristics to the application properties and the processor speed, during the execution of real applications there are times when the pr...
Aviral Shrivastava, Eugene Earlie, Nikil D. Dutt, ...
ISLPED
2004
ACM
123views Hardware» more  ISLPED 2004»
14 years 2 months ago
An efficient voltage scaling algorithm for complex SoCs with few number of voltage modes
Increasing demand for larger high-performance applications requires developing more complex systems with hundreds of processing cores on a single chip. To allow dynamic voltage sc...
Bita Gorjiara, Nader Bagherzadeh, Pai H. Chou
SIGGRAPH
2010
ACM
14 years 1 months ago
Multi-scale image harmonization
Traditional image compositing techniques, such as alpha matting and gradient domain compositing, are used to create composites that have plausible boundaries. But when applied to ...
Kalyan Sunkavalli, Micah K. Johnson, Wojciech Matu...
ISCA
2007
IEEE
111views Hardware» more  ISCA 2007»
14 years 3 months ago
Express virtual channels: towards the ideal interconnection fabric
Due to wire delay scalability and bandwidth limitations inherent in shared buses and dedicated links, packet-switched on-chip interconnection networks are fast emerging as the per...
Amit Kumar 0002, Li-Shiuan Peh, Partha Kundu, Nira...