In this paper we introduce Resizable Data Composer-Cache (RDC-Cache). This novel cache architecture operates correctly at sub 500 mV in 65 nm technology tolerating large number of...
Avesta Sasan, Houman Homayoun, Ahmed M. Eltawil, F...
Even after carefully tuning the memory characteristics to the application properties and the processor speed, during the execution of real applications there are times when the pr...
Aviral Shrivastava, Eugene Earlie, Nikil D. Dutt, ...
Increasing demand for larger high-performance applications requires developing more complex systems with hundreds of processing cores on a single chip. To allow dynamic voltage sc...
Traditional image compositing techniques, such as alpha matting and gradient domain compositing, are used to create composites that have plausible boundaries. But when applied to ...
Kalyan Sunkavalli, Micah K. Johnson, Wojciech Matu...
Due to wire delay scalability and bandwidth limitations inherent in shared buses and dedicated links, packet-switched on-chip interconnection networks are fast emerging as the per...
Amit Kumar 0002, Li-Shiuan Peh, Partha Kundu, Nira...