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» Cell architecture for nanoelectronic design
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ASPDAC
2000
ACM
80views Hardware» more  ASPDAC 2000»
13 years 12 months ago
An interleaved dual-battery power supply for battery-operated electronics
 After a detailed analysis and discussion of two important characteristics of today’s battery cells (i.e., their current-capacity and current-voltage curves), this paper descr...
Qing Wu, Qinru Qiu, Massoud Pedram
HPCA
2002
IEEE
14 years 8 months ago
Evaluation of a Multithreaded Architecture for Cellular Computing
Cyclops is a new architecture for high performance parallel computers being developed at the IBM T. J. Watson Research Center. The basic cell of this architecture is a single-chip...
Calin Cascaval, José G. Castaños, Lu...
DSN
2004
IEEE
13 years 11 months ago
The Recursive NanoBox Processor Grid: A Reliable System Architecture for Unreliable Nanotechnology Devices
Advanced molecular nanotechnology devices are expected to have exceedingly high transient fault rates and large numbers of inherent device defects compared to conventional CMOS de...
A. J. KleinOsowski, Kevin KleinOsowski, Vijay Rang...
DATE
2007
IEEE
99views Hardware» more  DATE 2007»
14 years 1 months ago
Very wide register: an asymmetric register file organization for low power embedded processors
In current embedded systems processors, multi-ported register files are one of the most power hungry parts of the processor, even when they are clustered. This paper presents a n...
Praveen Raghavan, Andy Lambrechts, Murali Jayapala...
DAC
2004
ACM
13 years 11 months ago
An SoC design methodology using FPGAs and embedded microprocessors
In System on Chip (SoC) design, growing design complexity has esigners to start designs at higher abstraction levels. This paper proposes an SoC design methodology that makes full...
Nobuyuki Ohba, Kohji Takano