285 search results - page 45 / 57 » Cell architecture for nanoelectronic design |
DAC
2002
ACM
14 years 8 months ago
2002
ACM
In this paper we propose a novel integrated circuit and architectural level technique to reduce leakage power consumption in high performance cache memories using single Vt (trans...
DAC
2009
ACM
14 years 4 days ago
2009
ACM
We present an unconventional clock distribution that emphasizes flexibility and layout independence. It suits a variety of applications, clock domain shapes and sizes using a modu...
ETT
2006
13 years 7 months ago
2006
Abstract-- The benefit of hybrid mobile communication networks combining point-to-point and point-to-multipoint systems should be an optimized transfer of data for both providers a...
VLSID
1993
IEEE
13 years 11 months ago
1993
IEEE
Low latency, application, specific multipliers are required for m,any DSP algorithms. Tree multipliers are an obvious answer to this requirement. However, tree architectures have ...
RTCSA
2005
IEEE
14 years 1 months ago
2005
IEEE
We propose a new architecture for a content protection system that conceals confidential data and algorithms in an FPGA as electrical circuits. This architecture is designed for a...