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VLSID
2002
IEEE
207views VLSI» more  VLSID 2002»
14 years 7 months ago
Synthesis of High Performance Low Power Dynamic CMOS Circuits
This paper presents a novel approach for the synthesis of dynamic CMOS circuits using Domino and Nora styles. As these logic styles can implement only non-inverting logic, convent...
Debasis Samanta, Nishant Sinha, Ajit Pal
MOBISYS
2004
ACM
14 years 7 months ago
Improving the Latency of 802.11 hand-offs using Neighbor Graphs
The 802.11 IEEE Standard has enabled low cost and effective wireless LAN services (WLAN). With the sales and deployment of WLAN based networks exploding, many people believe that ...
Minho Shin, Arunesh Mishra, William A. Arbaugh
DSD
2009
IEEE
118views Hardware» more  DSD 2009»
14 years 2 months ago
Internet-Router Buffered Crossbars Based on Networks on Chip
—The scalability and performance of the Internet depends critically on the performance of its packet switches. Current packet switches are based on single-hop crossbar fabrics, w...
Kees Goossens, Lotfi Mhamdi, Iria Varela Senin
ICPPW
2009
IEEE
14 years 2 months ago
Comparing and Optimising Parallel Haskell Implementations for Multicore Machines
—In this paper, we investigate the differences and tradeoffs imposed by two parallel Haskell dialects running on multicore machines. GpH and Eden are both constructed using the h...
Jost Berthold, Simon Marlow, Kevin Hammond, Abdall...
ISCAS
2006
IEEE
122views Hardware» more  ISCAS 2006»
14 years 1 months ago
256-channel integrated neural interface and spatio-temporal signal processor
Abstract- We present an architecture and VLSI implemen- Various strategies in the analysis of spatio-temporal dynamtation of a distributed neural interface and spatio-temporal ics ...
J. N. Y. Aziz, Roman Genov, B. R. Bardakjian, M. D...