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DATE
2006
IEEE
142views Hardware» more  DATE 2006»
14 years 1 months ago
Physical-aware simulated annealing optimization of gate leakage in nanoscale datapath circuits
For CMOS technologies below 65nm, gate oxide direct tunneling current is a major component of the total power dissipation. This paper presents a simulated annealing based algorith...
Saraju P. Mohanty, Ramakrishna Velagapudi, Elias K...
MOBIQUITOUS
2005
IEEE
14 years 1 months ago
Multi-Constraint Dynamic Access Selection in Always Best Connected Networks
Abstract— In future generation networks, various access technologies, such as Wi-Fi, Bluetooth, GPRS and UMTS, etc., are simultaneously available to mobile devices. They vary in ...
Bo Xing, Nalini Venkatasubramanian
ITC
2000
IEEE
124views Hardware» more  ITC 2000»
13 years 12 months ago
Wrapper design for embedded core test
A wrapper is a thin shell around the core, that provides the switching between functional, and core-internal and core-external test modes. Together with a test access mechanism (T...
Yervant Zorian, Erik Jan Marinissen, Maurice Lousb...
ISQED
2006
IEEE
107views Hardware» more  ISQED 2006»
14 years 1 months ago
On Optimizing Scan Testing Power and Routing Cost in Scan Chain Design
— With advanced VLSI manufacturing technology in deep submicron (DSM) regime, we can integrate entire electronic systems on a single chip (SoC). Due to the complexity in SoC desi...
Li-Chung Hsu, Hung-Ming Chen
DAC
1999
ACM
13 years 11 months ago
Behavioral Synthesis of Analog Systems Using Two-layered Design Space Exploration
This paper presents a novel approach for synthesis of analog systems from behavioral VHDL-AMS specifications. We implemented this approach in the VASE behavioral-synthesis tool. ...
Alex Doboli, Adrián Núñez-Ald...