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» Challenges in Embedded Memory Design and Test
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FPGA
2006
ACM
129views FPGA» more  FPGA 2006»
14 years 5 days ago
Power-aware RAM mapping for FPGA embedded memory blocks
Embedded memory blocks are important resources in contemporary FPGA devices. When targeting FPGAs, application designers often specify high-level memory functions which exhibit a ...
Russell Tessier, Vaughn Betz, David Neto, Thiagara...
DFT
2006
IEEE
203views VLSI» more  DFT 2006»
14 years 2 months ago
Self Testing SoC with Reduced Memory Requirements and Minimized Hardware Overhead
This paper describes a methodology of creating a built-in diagnostic system of a System on Chip and experimental results of the system application on the AT94K FPSLIC with cores d...
Ondrej Novák, Zdenek Plíva, Jiri Jen...
VTS
2005
IEEE
95views Hardware» more  VTS 2005»
14 years 2 months ago
SRAM Retention Testing: Zero Incremental Time Integration with March Algorithms
Testing data retention faults (DRFs), particularly in integrated systems on chip comprised of very large number of various sizes and types of embedded SRAMs is challenging and typ...
Baosheng Wang, Yuejian Wu, Josh Yang, André...
DAC
2000
ACM
14 years 9 months ago
System chip test: how will it impact your design?
A major challenge in realizing core-based system chips is the adoption and design-in of adequate test and diagnosis strategies. This tutorial paper discusses the specific challeng...
Yervant Zorian, Erik Jan Marinissen
DATE
2005
IEEE
155views Hardware» more  DATE 2005»
14 years 2 months ago
Studying Storage-Recomputation Tradeoffs in Memory-Constrained Embedded Processing
Fueled by an unprecedented desire for convenience and self-service, consumers are embracing embedded technology solutions that enhance their mobile lifestyles. Consequently, we wi...
Mahmut T. Kandemir, Feihui Li, Guilin Chen, Guangy...