658 search results - page 105 / 132 » Challenges in Physical Chip Design |
MICRO
2008
IEEE
14 years 3 months ago
2008
IEEE
Scaling of CMOS feature size has long been a source of dramatic performance gains. However, the reduction in voltage levels has not been able to match this rate of scaling, leadin...
DAC
2010
ACM
14 years 24 days ago
2010
ACM
We propose a parallel global routing algorithm that concurrently processes routing subproblems corresponding to rectangular subregions covering the chip area. The algorithm uses a...
TVLSI
2002
13 years 8 months ago
2002
Abstract--This paper provides a high level survey of the increasing effects of on-chip inductance. These effects are classified into desirable and nondesirable effects. Among the u...
EUROPKI
2009
Springer
13 years 6 months ago
2009
Springer
Efficient zero-knowledge proofs of knowledge (ZK-PoK) are basic building blocks of many cryptographic applications such as identification schemes, group signatures, and secure mult...
ICCAD
2009
IEEE
13 years 6 months ago
2009
IEEE
Boolean satisfiability (SAT) based methods have traditionally been popular for formally verifying properties for digital circuits. We present a novel methodology for formulating a...