658 search results - page 23 / 132 » Challenges in Physical Chip Design |
DATE
2004
IEEE
14 years 12 days ago
2004
IEEE
A challenge facing designers of systems on chip (SoC) containing networks on chip (NoC) is to find NoC instances that balance the cost (e.g. area) and performance (e.g. latency an...
ISPD
2006
ACM
14 years 2 months ago
2006
ACM
Physical Design of modern systems on chip is extremely challenging. Such digital integrated circuits often contain tens of millions of logic gates, intellectual property blocks, e...
MOBICOM
1999
ACM
14 years 1 months ago
1999
ACM
A key challenge facing wireless networking is to utilize the spectrum as e ciently as possible given current channel conditions and in the most e ective way for each application. ...
DAC
2001
ACM
14 years 9 months ago
2001
ACM
Using on-chip interconnection networks in place of ad-hoc global wiring structures the top level wires on a chip and facilitates modular design. With this approach, system modules...
ISCA
2006
IEEE
14 years 2 months ago
2006
IEEE
The physical layer of most wireless protocols is traditionally implemented in custom hardware to satisfy the heavy computational requirements while keeping power consumption to a ...