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» Challenges in Physical Chip Design
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ISLPED
2006
ACM
70views Hardware» more  ISLPED 2006»
14 years 2 months ago
Sub-threshold design: the challenges of minimizing circuit energy
In this paper, we identify the key challenges that oppose subthreshold circuit design and describe fabricated chips that verify techniques for overcoming the challenges. Categorie...
Benton H. Calhoun, Alice Wang, Naveen Verma, Anant...
DATE
2007
IEEE
143views Hardware» more  DATE 2007»
14 years 3 months ago
Portable multimedia SoC design: a global challenge
- The intrinsic capability brought by each new technology node opens the way to a broad range of system integration options and continuously enables new applications to be integrat...
Maurizio Paganini, Georg Kimmich, Stephane Ducrey,...
ASPDAC
1998
ACM
86views Hardware» more  ASPDAC 1998»
14 years 26 days ago
Hierarchy - A CHDStd Tool for the Coming Deep Submicron Complex Design Crisis
Abstract -- This paper describes the use of a hierarchical design representation standard, CHDStd, as part of the architecture of the Chip Hierarchical Design System (CHDS). Detail...
S. Grout, G. Ledenbach, R. G. Bushroe, P. Fisher, ...
DAC
2007
ACM
14 years 9 months ago
Physical Unclonable Functions for Device Authentication and Secret Key Generation
Physical Unclonable Functions (PUFs) are innovative circuit primitives that extract secrets from physical characteristics of integrated circuits (ICs). We present PUF designs that...
G. Edward Suh, Srinivas Devadas
NOCS
2007
IEEE
14 years 2 months ago
NoC Design and Implementation in 65nm Technology
As embedded computing evolves towards ever more powerful architectures, the challenge of properly interconnecting large numbers of on-chip computation blocks is becoming prominent...
Antonio Pullini, Federico Angiolini, Paolo Meloni,...