658 search results - page 78 / 132 » Challenges in Physical Chip Design |
DATE
2008
IEEE
14 years 3 months ago
2008
IEEE
The NETWORK-ON-CHIP (NOC) interconnection paradigm has been gaining momentum thanks to its flexibility, scalability and suitability to deep submicron technology processes. The ne...
VTS
2008
IEEE
14 years 3 months ago
2008
IEEE
Dealing with static and dynamic parameter variations has become a major challenge for design and test. To avoid unnecessary yield loss and to ensure reliable system operation a ro...
EUROPAR
2008
Springer
13 years 10 months ago
2008
Springer
Chip multiprocessors designed for streaming applications such as Cell BE offer impressive peak performance but suffer from limited bandwidth to offchip main memory. As the number o...
DATE
2008
IEEE
14 years 3 months ago
2008
IEEE
We present a novel methodology for design space exploration using a two-steps scheme to optimize the number of virtual channel buffers (buffers take the premier share of the route...
VLSID
2004
IEEE
14 years 9 months ago
2004
IEEE
Recent developments in embedded systems technology have opened up a vast area of research and development- the development of portable and affordable assistive devices tuned to sp...