658 search results - page 82 / 132 » Challenges in Physical Chip Design |
EUC
2006
Springer
14 years 15 days ago
2006
Springer
Abstract. When flash memory is used as a storage in embedded systems, block level translation layer is required between conventional filesystem and flash memory chips due to its ph...
SIGITE
2006
ACM
14 years 2 months ago
2006
ACM
Delivery of content in networking and system administration curricula involves significant hands-on laboratory experience supplementing traditional classroom instruction at the Ro...
ICCAD
2004
IEEE
14 years 5 months ago
2004
IEEE
As the technology progresses, interconnect delays have become bottlenecks of chip performance. Three dimensional (3D) integrated circuits are proposed as one way to address this p...
ISQED
2010
IEEE
14 years 3 months ago
2010
IEEE
Leakage power has grown significantly and is a major challenge in SoC design. Among SoC's components, clock distribution network power accounts for a large portion of chip po...
ASAP
2008
IEEE
14 years 3 months ago
2008
IEEE
As semiconductor processing technology continues to scale down, managing reliability becomes an increasingly difficult challenge in high-performance microprocessor design. Transie...