658 search results - page 8 / 132 » Challenges in Physical Chip Design |
IPPS
2003
IEEE
14 years 1 months ago
2003
IEEE
Tiled architectures can provide a model for early estimation of global interconnect costs. A design exploration tool for reconfigurable architectures is currently under developmen...
ASPDAC
2006
ACM
14 years 2 months ago
2006
ACM
- Although the emerging three-dimensional integration technology can significantly reduce interconnect delay, chip area, and power dissipation in nanometer technologies, its impact...
NOCS
2007
IEEE
14 years 2 months ago
2007
IEEE
We present a novel network-on-chip-based architecture for future programmable chips (FPGAs). A key challenge for FPGA design is supporting numerous highly variable design instance...
CODES
2007
IEEE
14 years 3 months ago
2007
IEEE
High-end biomedical applications are a good target for specificpurpose system-on-chip (SoC) implementations. Human heart electrocardiogram (ECG) real-time monitoring and analysis ...
ASPDAC
2009
ACM
14 years 3 months ago
2009
ACM
Three-dimensional stacking of silicon layers is emerging as a promising solution to handle the design complexity and heterogeneity of Systems on Chips (SoCs). Networks on Chips (N...